`timescale 1us/1us
module uart_byte_tx_tb ();
    reg clk;
    reg[7:0] byte;
    reg reset;
    wire led;
    wire tx;
    uart_byte_tx uart_byte_tx(
        .clk(clk),
        .byte(byte),
        .reset(reset),
        .tx(tx),
        .tx_led(led)
    );
    defparam uart_byte_tx.contmax=10;
    defparam uart_byte_tx.witemax=50;
    initial begin
            clk<=0;
            reset<=0;
            byte<=8'b11001100;
    #10     reset<=1;
    #200    byte<=8'b10101010;
    #200    byte<=8'b01101101;
    #200    byte<=8'b11100011;

    #9000   $stop;
   end

   always #1 clk<=~clk;
endmodule
